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R5F72115D160FPV Datasheet(PDF) 62 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 62 Page - Renesas Technology Corp |
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62 / 1228 page  Section 2 CPU Rev. 2.00 May. 08, 2008 Page 38 of 1200 REJ09B0344-0200 Classification Types Operation Code Function No. of Instructions 14 CLRT T bit clear 36 CLRMAC MAC register clear System control LDBANK Register restoration from specified register bank entry LDC Load to control register LDS Load to system register NOP No operation RESBANK Register restoration from register bank RTE Return from exception handling SETT T bit set SLEEP Transition to power-down mode STBANK Register save to specified register bank entry STC Store control register data STS Store system register data TRAPA Trap exception handling 10 BAND Bit AND 14 Bit manipulation BCLR Bit clear BLD Bit load BOR Bit OR BSET Bit set BST Bit store BXOR Bit exclusive OR BANDNOT Bit NOT AND BORNOT Bit NOT OR BLDNOT Bit NOT load Total: 91 197 |
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