R5F72115D160FPV datasheet(94/1228 Pages) RENESAS

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Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 May. 08, 2008 Page 70 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

6 to 4

IFC[2:0]

000

R/W

Internal Clock (I

φ) Frequency Division Ratio

These bits specify the frequency division ratio of the

internal clock with respect to the output frequency of

PLL circuit 1.

If a prohibited value is specified, correct operation

cannot be guaranteed.

000:

× 1 time

001:

× 1/2 time

011:

× 1/4 time

Other than above: Setting prohibited

RNGS

R/W

Set this bit according to the output frequency of PLL

circuit 1.

0: High-frequency mode

1: Low-frequency mode

Always specify high-frequency mode for this LSI.

Do not set this bit to 1.

2 to 0

PFC[2:0]

011

R/W

Peripheral Clock (P

φ) Frequency Division Ratio

These bits specify the frequency division ratio of the

peripheral clock with respect to the output frequency

of PLL circuit 1.

If a prohibited value is specified, correct operation

cannot be guaranteed.

000:

× 1 time

001:

× 1/2 time

011:

× 1/4 time

101:

× 1/8 time

Other than above: Setting prohibited

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