R5F72115D160FPV datasheet(35/1228 Pages) RENESAS

35 / 1228 page

Section 1 Overview

Rev. 2.00 May. 08, 2008 Page 11 of 1200

REJ09B0344-0200

Classification

Symbol

I/O

Name

Function

NMI

Non-maskable

interrupt

Non-maskable interrupt request pin.

Fix it high when not in use.

IRQ7 to IRQ0

Interrupt requests

7 to 0

Maskable interrupt request pins.

Level-input or edge-input detection

can be selected. When the edge-

input detection is selected, the rising

edge, falling edge, or both edges can

also be selected.

Interrupts

IRQOUT

Interrupt request

output

Indicates that an interrupt has

occurred, enabling external devices

to be informed of an interrupt

occurrence even while the bus

mastership is released.

Address bus

A25 to A0

Address bus

Outputs addresses.

Data bus

D15 to D0

I/O

Data bus

Bidirectional data bus.

CS7 to CS0

Chip select 7 to 0 Chip-select signals for external

memory or devices.

Read

Indicates that data is read from an

external device.

RD/

Read/write

Read/write signal.

Bus start

Bus-cycle start signal.

Address hold

Address hold timing signal for the

device that uses the address/data-

multiplexed bus.

WAIT

Wait

Input signal for inserting a wait cycle

into the bus cycles during access to

the external space.

Bus control

WE0

Byte select

Indicates a write access to bits 7 to 0

of data of external memory or

device.

WE1

Byte select

Indicates a write access to bits 15 to

8 of data of external memory or

device.

R5F72115D160FPV Datasheet(PDF) 35 Page - Renesas Technology Corp

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