R5F72115D160FPV datasheet(93/1228 Pages) RENESAS

93 / 1228 page

Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 May. 08, 2008 Page 69 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

CKOEN

R/W

Clock Output Enable

Specifies whether a clock is output on the CK pin, or

the CK pin is placed in the level-fixed state during

software standby mode or when exiting software

standby mode.

If this bit is cleared to 0, the CK pin is fixed to the low

level during software standby mode or when exiting

software standby mode. Therefore, the malfunction of

an external circuit because of an unstable CK clock

upon exit from software standby mode can be

prevented.

0: The CK pin is fixed to the low level during software

standby mode or when exiting software standby

mode.

1: Clock is output from the CK pin (placed in the high-

impedance state during software standby mode).

11, 10

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

9, 8

STC[1:0]

R/W

Frequency multiplication ratio of PLL circuit 1

00:

× 1 time

01:

× 2 times

10: Setting prohibited

11:

× 4 times

⎯

Reserved

This bit is always read as 0. The write value should

always be 0.

R5F72115D160FPV Datasheet(PDF) 93 Page - Renesas Technology Corp

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