R5F72115D160FPV datasheet(92/1228 Pages) RENESAS

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Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 May. 08, 2008 Page 68 of 1200

REJ09B0344-0200

4.4

The clock pulse generator has the following registers.

Table 4.4

Abbreviation R/W

Initial Value Address

Access Size

Frequency control register

FRQCR

R/W

H'1003

H'FFFE0010 16

MTU2S clock frequency

control register

MCLKCR

R/W

H'43

H'FFFE0410 8

AD clock frequency control

ACLKCR

R/W

H'43

H'FFFE0414 8

4.4.1

Frequency Control Register (FRQCR)

FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the

CK pin in software standby mode, the frequency multiplication ratio of PLL circuit 1, and the

frequency division ratio of the internal clock (I

φ) and peripheral clock (Pφ). Only word access can

be used on FRQCR.

FRQCR is initialized to H'1003 only by a power-on reset. FRQCR retains its previous value by a

manual reset or in software standby mode. The previous value is also retained when an internal

reset is triggered by an overflow of the WDT.

0001000000000011

R/W

Bit:

Initial value:

R/W:

CKOEN

STC[1:0]

IFC[2:0]

RNGS

PFC[2:0]

Bit

Bit Name

Initial

Value

R/W

Description

15 to 13

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

R5F72115D160FPV Datasheet(PDF) 92 Page - Renesas Technology Corp

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