R5F72115D160FPV datasheet(87/1228 Pages) RENESAS

87 / 1228 page

Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 May. 08, 2008 Page 63 of 1200

REJ09B0344-0200

The clock pulse generator blocks function as follows:

(1)

PLL Circuit 1

PLL circuit 1 multiplies the input clock frequency from the CK pin by 1, 2, or 4. The

multiplication rate is set by the frequency control register. When this is done, the phase of the

rising edge of the internal clock (I

φ) is controlled so that it will agree with the phase of the rising

edge of the CK pin.

(2)

PLL Circuit 2

PLL circuit 2 multiplies the input clock frequency from the crystal oscillator or EXTAL pin by 4.

The multiplication rate is fixed according to the clock operating mode. The clock operating mode

is specified by the MD_CLK0 and MD_CLK2 pins. For details on the clock operating mode, see

table 4.2.

(3)

Crystal Oscillator

The crystal oscillator is an oscillation circuit in which a crystal resonator is connected to the

XTAL pin or EXTAL pin. This can be used according to the clock operating mode.

(4)

Divider 1

Divider 1 generates a clock signal at the operating frequency used by the internal clock (I

φ), the

bus clock (B

φ), the peripheral clock (Pφ), the MTU2S clock (Mφ), or the AD clock (Aφ). The

operating frequency can be 1, 1/2, 1/4, or 1/8 times the output frequency of PLL circuit 1.

However, set the internal clock (I

φ) so that its frequency is not less than the clock frequency of the

CK pin, and set the peripheral clock (P

φ) so that its frequency is not more than the clock frequency

of the CK pin. The division ratio is set in the frequency control register (FRQCR).

(5)

Clock Frequency Control Circuit

The clock frequency control circuit controls the clock frequency using the MD_CLK0 and

MD_CLK2 pins and the frequency control register (FRQCR).

R5F72115D160FPV Datasheet(PDF) 87 Page - Renesas Technology Corp