R5F72115D160FPV datasheet(31/1228 Pages) RENESAS

31 / 1228 page

Section 1 Overview

Rev. 2.00 May. 08, 2008 Page 7 of 1200

REJ09B0344-0200

1.2

Block Diagram

SH-2A

CPU core

WAVE

interface

(WAVEIF)

WAVE input/output

CPU bus

(C bus)

(I clock)

ROM

Cache

On-chip ROM

512 Kbytes

On-chip RAM

32 Kbytes

User break

controller

(UBC)

Advanced

user debuger II

(AUD-II)

Bus state

controller

(BSC)

Peripheral

bus controller

Direct memory

access controller

(DMAC)

Pin function

controller

(PFC)

I/O ports

Clock pulse

generator (CPG)

Interrupt

controller

(INTC)

Multi-function

timer pulse

unit 2

subset

(MTU2S)

Multi-function

timer pulse

unit 2

(MTU2)

Port output

enable 2

(POE2)

Compare

match timer

(CMT)

CPU memory access bus (M bus)

Internal bus (I bus) (B clock)

Peripheral bus (P clock)

Port

General input/output

EXTAL input,

XTAL output,

CK input/output,

Clock mode input

RES input,

MRES input,

NMI input,

IRQ input,

IRQOUT output

Timer pulse

input/output

Timer pulse

input/output

POE input

Port

External bus input/output

External bus width mode input

UBCTRG output

DREQ input

DACK output

TEND output

Watchdog

timer

(WDT)

Port

WDTOVF output

Serial

communication

interface

with FIFO

(SCIF)

Port

Serial input/output

I2C bus

interface 3

(IIC3)

Port

I2C bus

input/output

12-bit

A/D converter

(ADC)

Port

Analog input,

ADTRG input

8-bit

D/A converter

(DAC)

Port

Analog output

Power-down

mode

control

High-performance

user debugging

interface

(H-UDI)

Port

JTAG input/output

CPU instruction fetch bus (F bus)

Figure 1.1 Block Diagram

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