R5F72115D160FPV datasheet(361/1228 Pages) RENESAS

361 / 1228 page

Section 9 Direct Memory Access Controller (DMAC)

Rev. 2.00 May. 08, 2008 Page 337 of 1200

REJ09B0344-0200

(1)

Address Modes

(a)

Dual Address Mode

In dual address mode, both the transfer source and destination are accessed (selected) by an

address. The transfer source and destination can be located externally or internally.

DMA transfer requires two bus cycles because data is read from the transfer source in a data read

cycle and written to the transfer destination in a data write cycle. At this time, transfer data is

temporarily stored in the DMAC. In the transfer between external memories as shown in figure

9.5, data is read to the DMAC from one external memory in a data read cycle, and then that data is

written to the other external memory in a data write cycle.

Data buffer

Memory

Transfer source

module

Transfer destination

module

Memory

Transfer source

module

Transfer destination

module

SAR

DAR

Data buffer

SAR

DAR

The SAR value is an address, data is read from the transfer source module,

and the data is tempolarily stored in the DMAC.

First bus cycle

Second bus cycle

The DAR value is an address and the value stored in the data buffer in the

DMAC is written to the transfer destination module.

DMAC

Figure 9.5 Data Flow of Dual Address Mode

Auto request, external request, and on-chip peripheral module request are available for the transfer

request. DACK can be output in read cycle or write cycle in dual address mode. The AM bit in the

channel control register (CHCR) can specify whether the DACK is output in read cycle or write

cycle.

Figure 9.6 shows an example of DMA transfer timing in dual address mode.

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