EP4CE40 datasheet(248/488 Pages) ALTERA

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Chapter 9: SEU Mitigation in Cyclone IV Devices

User Mode Error Detection

Cyclone IV Device Handbook,

May 2013

Altera Corporation

Volume 1

Configuration error detection determines if the configuration data received through

an external memory device is corrupted during configuration. To validate the

configuration data, the Quartus® II software uses a function to calculate the CRC

value for each configuration data frame and stores the frame-based CRC value in the

configuration data as part of the configuration bit stream.

During configuration, Cyclone IV devices use the same methodology to calculate the

CRC value based on the frame of data that is received and compares it against the

frame CRC value in the data stream. Configuration continues until either the device

detects an error or all the values are calculated.

In addition to the frame-based CRC value, the Quartus II software generates a 32-bit

CRC value for the whole configuration bit stream. This 32-bit CRC value is stored in

the 32-bit storage register at the end of the configuration and is used for user mode

error detection that is discussed in “User Mode Error Detection”.

User Mode Error Detection

1 User mode error detection is available in Cyclone IV GX and Cyclone IV E devices

with 1.2-V core voltage. Cyclone IV E devices with 1.0-V core voltage do not support

user mode error detection.

Soft errors are changes in a configuration random-access memory (CRAM) bit state

due to an ionizing particle. Cyclone IV devices have built-in error detection circuitry

to detect data corruption by soft errors in the CRAM cells.

This error detection capability continuously computes the CRC of the configured

CRAM bits based on the contents of the device and compares it with the

pre-calculated CRC value obtained at the end of the configuration. If the CRCs match,

there is no error in the current configuration CRAM bits. The process of error

detection continues until the device is reset (by setting nCONFIG to low).

The Cyclone IV device error detection feature does not check memory blocks and I/O

buffers. These device memory blocks support parity bits that are used to check the

contents of memory blocks for any error. The I/O buffers are not verified during error

detection because the configuration data uses flip-flops as storage elements that are

more resistant to soft errors. Similar flip-flops are used to store the pre-calculated CRC

and other error detection circuitry option bits.

The error detection circuitry in Cyclone IV devices uses a 32-bit CRC IEEE 802

standard and a 32-bit polynomial as the CRC generator. Therefore, a single 32-bit CRC

calculation is performed by the device. If a soft error does not occur, the resulting

32-bit signature value is 0x00000000, that results in a 0 on the CRC_ERROR output

signal. If a soft error occurs in the device, the resulting signature value is non-zero and

the CRC_ERROR output signal is 1.

You can inject a soft error by changing the 32-bit CRC storage register in the CRC

circuitry. After verifying the induced failure, you can restore the 32-bit CRC value to

the correct CRC value with the same instruction and inserting the correct value.

1 Before updating it with a known bad value, Altera recommends reading out the

correct value.

EP4CE40 Datasheet(PDF) 248 Page - Altera Corporation

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