EP4CE40 datasheet(255/488 Pages) ALTERA

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Chapter 9: SEU Mitigation in Cyclone IV Devices

9–9

Recovering from CRC Errors

May 2013

Altera Corporation

Cyclone IV Device Handbook,

Volume 1

Table 9–7 lists the input and output ports that you must include in the atom.

Recovering from CRC Errors

The system that the Altera FPGA resides in must control device reconfiguration. After

detecting an error on the CRC_ERROR pin, strobing the nCONFIG low directs the system

to perform the reconfiguration at a time when it is safe for the system to reconfigure

the FPGA.

When the data bit is rewritten with the correct value by reconfiguring the device, the

device functions correctly.

While soft errors are uncommon in Altera devices, certain high-reliability applications

might require a design to account for these errors.

Table 9–7. CRC Block Input and Output Ports

Port

Input/Output

Definition

<crcblock_name>

Input

Unique identifier for the CRC block, and represents any identifier name that is legal

for the given description language (for example, Verilog HDL, VHDL, and AHDL).

This field is required.

.clk(<clock source>

Input

This signal designates the clock input of this cell. All operations of this cell are

with respect to the rising edge of the clock. Whether it is the loading of the data

into the cell or data out of the cell, it always occurs on the rising edge. This port is

required.

.shiftnld

shiftnld

source>)

Input

This signal is an input into the error detection block. If shiftnld=1, the data is

shifted from the internal shift register to the regout at each rising edge of clk. If

shiftnld=0

, the shift register parallel loads either the pre-calculated CRC value

or the update register contents, depending on the ldsrc port input. To do this,

the shiftnld must be driven low for at least two clock cycles. This port is

required.

.ldsrc

ldsrc

source>)

Input

This signal is an input into the error detection block. If ldsrc=0, the

pre-computed CRC register is selected for loading into the 32-bit shift register at

the rising edge of clk when shiftnld=0. If ldsrc=1, the signature register

(result of the CRC calculation) is selected for loading into the shift register at the

rising edge of clk when shiftnld=0. This port is ignored when

shiftnld=1

. This port is required.

.crcerror

crcerror

indicator

output>)

Output

This signal is the output of the cell that is synchronized to the internal oscillator of

the device (80-MHz internal oscillator) and not to the clk port. It asserts high if

the error block detects that a SRAM bit has flipped and the internal CRC

computation has shown a difference with respect to the pre-computed value. You

must connect this signal either to an output pin or a bidirectional pin. If it is

connected to an output pin, you can only monitor the CRC_ERROR pin (the core

cannot access this output). If the CRC_ERROR signal is used by core logic to

read error detection logic, you must connect this signal to a BIDIR pin. The

signal is fed to the core indirectly by feeding a BIDIR pin that has its output

enable port connected to VCC (see Figure 9–3 on page 9–8).

.regout

registered

output>)

Output

This signal is the output of the error detection shift register synchronized to the

clk

port to be read by core logic. It shifts one bit at each cycle, so you should

clock the clk signal 31 cycles to read out the 32 bits of the shift register.

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