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UM0434 Datasheet(PDF) 6 Page - STMicroelectronics

Part # UM0434
Description  The primary objective of this user?셲 manual is to describe
PDF  390 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UM0434 Datasheet(HTML) 6 Page - STMicroelectronics

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Table of contents
UM0434
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6.6.4
Instruction storage interrupt (IVOR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.6.5
External input interrupt (IVOR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.6.6
Alignment interrupt (IVOR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.6.7
Program interrupt (IVOR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.6.8
Floating-Point unavailable interrupt (IVOR7) . . . . . . . . . . . . . . . . . . . . 175
6.6.9
System call interrupt (IVOR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.6.10
Auxiliary processor unavailable interrupt (IVOR9) . . . . . . . . . . . . . . . . 176
6.6.11
Decrementer interrupt (IVOR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.6.12
Fixed-Interval timer interrupt (IVOR11) . . . . . . . . . . . . . . . . . . . . . . . . 177
6.6.13
Watchdog timer interrupt (IVOR12) . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.6.14
Data TLB error interrupt (IVOR13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.6.15
Instruction TLB error interrupt (IVOR14) . . . . . . . . . . . . . . . . . . . . . . . 179
6.6.16
Debug interrupt (IVOR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.6.17
System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.6.18
SPE APU unavailable interrupt (IVOR32) . . . . . . . . . . . . . . . . . . . . . . 183
6.6.19
SPE Floating-Point data interrupt (IVOR33) . . . . . . . . . . . . . . . . . . . . 184
6.6.20
SPE Floating-Point round interrupt (IVOR34) . . . . . . . . . . . . . . . . . . . 185
6.7
Exception recognition and priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
6.7.1
Interrupt priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
6.8
Interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.8.1
Enabling and disabling exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.8.2
Returning from an interrupt handler . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.9
Process switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
7
Memory management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.1.1
MMU features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.1.2
TLB entry maintenance features summary . . . . . . . . . . . . . . . . . . . . . 192
7.2
Effective to real address translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
7.2.1
Effective addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
7.2.2
Address spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
7.2.3
Virtual addresses and process ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
7.2.4
Translation flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
7.2.5
Permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.3
Translation lookaside buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.3.1
IPROT invalidation protection in TLB1 . . . . . . . . . . . . . . . . . . . . . . . . . 198



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