UM0434 datasheet(85/390 Pages) STMICROELECTRONICS

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UM0434

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4.13.2

Hardware implementation dependent register 1 (HID1)

The HID1 register is used for bus configuration and system control. HID1 is shown in

Table 61.

DCLREE

Debug interrupt clears MSR[EE]. Controls whether debug interrupts force external input

interrupts to be disabled, or whether they remain unaffected.

0 MSR[EE] unaffected by debug interrupt.

1 MSR[EE] cleared by debug interrupt.

DCLRCE

Debug interrupt clears MSR[CE]. Controls whether debug interrupts force critical interrupts to

be disabled, or whether they remain unaffected.

0 MSR[CE] unaffected by debug interrupt.

1 MSR[CE] cleared by debug Interrupt.

CICLRDE

Critical interrupt clears MSR[DE]. Controls whether certain critical interrupts (critical input,

watchdog timer) force debug interrupts to be disabled, or whether they remain unaffected.

Machine check interrupts have a separate control bit.

0 MSR[DE] unaffected by critical class interrupt.

1 MSR[DE] cleared by critical class interrupt.

If critical interrupt debug events are enabled (DBCR0[CIRPT] is set, which should only be

done when the debug APU is enabled), and MSR[DE] is set at the time of a critical interrupt

(critical input, watchdog timer), a debug event is generated after the critical interrupt handler

has been fetched, and the debug handler is executed first. In this case, DSRR0[DE] will have

been cleared, such that after returning from the debug handler, the critical interrupt handler

will not be run with MSR[DE] enabled.

MCCLRDE

Machine check interrupt clears MSR[DE]. Controls whether machine check interrupts force

debug interrupts to be disabled or are unaffected. If critical interrupt debug events are

enabled (DBCR0[CIRPT] is set, which should only be done when the debug APU is enabled),

and MSR[DE] is set at the time of a machine check interrupt, a debug event is generated after

the machine check interrupt handler is fetched, and the debug handler executes first. In this

case, DSRR0[DE] is cleared so that after returning from the debug handler, the machine

check handler cannot be run if MSR[DE] = 1.

0 MSR[DE] unaffected by machine check interrupt.

1 MSR[DE] cleared by machine check interrupt.

DAPUEN

Debug APU enable. Controls whether the debug APU is enabled.

0 Debug APU disabled. Debug interrupts use the critical interrupt resources: CSRR0/CSRR1

and rfci; rfdi is treated as an illegal instruction. DCLREE, DCLRCE, CICLRDE, and

MCCLRDE settings are ignored and are assumed to be ones.

1 Debug APU enabled. Debug interrupts use DSRR0/DSRR1 for saving state and rfdi is

available for returning from a debug interrupt.

Read and write access to DSRR0/DSRR1 via mfspr and mtspr is not affected by this bit.

56–63

—

Reserved, should be cleared.

Table 60.

HID0 field descriptions (continued)

Bits

Name

Description

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