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UM0434 Datasheet(PDF) 8 Page - STMicroelectronics

Part # UM0434
Description  The primary objective of this user?셲 manual is to describe
PDF  390 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UM0434 Datasheet(HTML) 8 Page - STMicroelectronics

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Table of contents
UM0434
8/391
8.3.6
Basic Multi-Cycle instruction pipeline operation . . . . . . . . . . . . . . . . . 214
8.3.7
Additional examples of instruction pipeline operation for load & store . 214
8.3.8
Move to/from SPR instruction pipeline operation . . . . . . . . . . . . . . . . . 215
8.4
Stalls caused by accessing SPRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
8.5
Instruction serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
8.6
Interrupt recognition and exception processing . . . . . . . . . . . . . . . . . . . 218
8.7
Instruction timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.7.1
SPE and embedded Floating-Point instruction timing . . . . . . . . . . . . . 226
8.8
Operand placement on performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
9
External core complex interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
9.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
9.2
Signal index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
9.3
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
9.3.1
Processor state signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
9.3.2
JTAG ID signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
9.4
Internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
9.5
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
9.5.1
Processor Instruction/Data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . 265
9.5.2
Burst accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
9.5.3
Address retraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
9.5.4
Address retraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
9.5.5
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
9.5.6
Interrupt interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
10
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
10.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
10.1.1
Power management signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
10.1.2
Power management control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
10.1.3
Software considerations for power management . . . . . . . . . . . . . . . . . 294
10.1.4
Debug considerations for power management . . . . . . . . . . . . . . . . . . 295
11
Debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
11.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
11.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
11.2.1
Software debug facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296



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