UM0434 datasheet(87/390 Pages) STMICROELECTRONICS

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UM0434

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4.15

L1 cache configuration registers

This section describes the register that helps not to configure the cache.

4.15.1

L1 cache configuration register 0 (L1CFG0)

The L1 cache configuration register 0 (L1CFG0) provides information on how not to

configure the e200z3 cache design. For e200z3, reads of this register return a value of all

zeros.

4.16

MMU registers

This section describes the e200z3 registers for setting up and maintaining the TLBs.

4.16.1

MMU control and status register 0 (MMUCSR0)

MMUCSR0, shown in

Table 65, controls the state of the MMU.

The MMUCSR0 fields are described in

Table 66.

Table 64.

Branch unit control and status register

Bits

Name

Description

32–53

—

Reserved, should be cleared.

BBFI

Branch target buffer flash invalidate. When set, BBFI flash clears the valid bit of all

BTB entries; clearing occurs regardless of the value of the enable bit (BPEN).

Note: BBFI is always read as 0.

55–62

—

Reserved, should be cleared.

BPEN

Branch target buffer (BTB) enable.

0 BTB prediction disabled. No hits are generated from the BTB and no new

entries are allocated. Entries are not automatically invalidated when BPEN

is cleared; BBFI controls entry invalidation.

1 BTB prediction enabled (enables BTB to predict branches).

Table 65.

MMU Control and Status Register 0 (MMUCSR0)

Field

—

TLB1_FI —

Reset

All zeros

R/W

SPR

SPR 1012

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