UM0434 datasheet(96/390 Pages) STMICROELECTRONICS

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MMUCFG[NPIDS]. (The e200z3 defines no additional PID registers.) PID values are used

to construct virtual addresses for accessing memory.

4.17

Support for fast context switching

To provide real-time capabilities for embedded systems, future versions of the e200z3 core

will include optional hardware support for fast context switching. The initial version of the

e200z3 does not implement additional register contexts.

4.17.1

Context control register (CTXCR)

The future versions of the e200z3 core may include optional hardware support for fast

context switching to provide real-time capabilities for embedded systems. The initial version

of e200z3 does not implement additional register contexts. A new privileged 32-bit special-

purpose register (SPR) called the context control register (CTXCR) is defined in the core

CPU. The CTXCR controls the context registers that are mapped to the current context and

holds current, alternate, and saved context information. Supervisor software reads the

CTXCR to determine whether multiple contexts are supported in hardware, and if so, the

number implemented. When multiple register contexts are present (CTXCR[NUMCTX] is

non-zero), CTXCR is also writable. Otherwise, writes are ignored, and the register reads as

all zeros. CTXCR is shown in

Table 86.

4.18

SPR register access

SPRs are accessed with the mfspr and mtspr instructions. The following sections outline

additional access requirements.

4.18.1

Invalid SPR references

System behavior when an invalid SPR is referenced depends on the apparent privilege level

of the register, which is determined by bit 5 in the SPR address. If the invalid SPR is

Table 85.

Process ID register (PID0)

55 56

Field

—

Process ID

Reset

All zeros

R/W

SPR

SPR 48

Table 86.

Context control register (CTXCR)

55 56

Field

—

Reset

All zeros

R/W

R/W (Writes are ignored because no additional contexts are implemented.)

SPR

SPR 560

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