UM0434 datasheet(20/390 Pages) STMICROELECTRONICS

20 / 390 page

Organization

UM0434

20/391

Organization

Following is a summary and a brief description of the major sections of this manual:

●

Chapter 3: e200z3 core complex overview on page 24,” provides a general description

of e200z3 functionality.

●

Chapter 4: Register model on page 38,” is useful for software engineers who need to

understand the programming model for the three programming environments and the

functionality of each register.

●

Chapter 5: Instruction model on page 108,” provides an overview of the addressing

modes and a description of the instructions. Instructions are organized by function.

●

Chapter 6: Interrupts and exceptions on page 160,” describes how the e200z3

implements the interrupt model as it is defined by the Book E architecture.

●

Chapter 7: Memory management unit on page 192,” provides specific hardware and

software details regarding the e200z3 MMU implementation.

●

Chapter 8: Instruction pipeline and execution timing on page 206,” describes how

instructions are fetched, decoded, issued, executed, completed, and how instruction

results are presented to the processor and memory system. Tables are provided that

indicate latency and throughput for each of the instructions supported by the e200z3.

●

Chapter 9: External core complex interfaces on page 235,” describes those aspects of

the CCB that are configurable or that provide status information through the

programming interface. It provides a glossary of signals mentioned throughout the book

to offer a clearer understanding of how the core is integrated as part of a larger device.

●

Chapter 10: Power management on page 292,” describes the power management

facilities as they are defined by Book E and implemented in the e200z3 core.

●

Chapter 11: Debug support on page 296,” describes the debug facilities as they are

defined by Book E and implemented in the e200z3 core.

●

Chapter 12: Nexus3 module on page 329,” describes the e200z3 Nexus3 module,

which provides real-time development capabilities for e200z3 processors in compliance

with the

IEEE-ISTO Nexus 5001-2003 standard.

●

This book also includes an index.

1.1

Bibliography

The following documentation, published by Morgan-Kaufmann Publishers, 340 Pine Street,

Sixth Floor, San Francisco, CA, provides useful information about the PowerPC architecture

and computer architecture in general:

●

The PowerPC Architecture: A Specification for a New Family of RISC Processors,

Second Edition, by International Business Machines, Inc.

For updates to the specification, see http://www.austin.ibm.com/tech/ppc-chg.html

●

Computer Architecture: A Quantitative Approach, Third Edition, by John L. Hennessy

and David A. Patterson.

●

Computer Organization and Design: The Hardware/Software Interface, Second Edition,

David A. Patterson and John L. Hennessy.

Note:

It is assumed that the reader understands operating systems, microprocessor system

design, and the basic principles of RISC processing.

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