UM0434 datasheet(65/390 Pages) STMICROELECTRONICS

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UM0434

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4.11.2

Timer status register (TSR)

TSR, shown in

Table 42, provides status information for the CPU timer facilities. EREF

describes the TSR in detail. TSR[WRS] is defined as implementation-dependent.

Writing zeros to them has no effect.

The TSR fields are described in

Table 43.

47–50

FPEXT

Fixed-interval timer period extension (see description for FP). FPEXT | FP select one of the 64

TB bits used to signal a fixed-interval timer exception.

51–63

—

Reserved, should be cleared.

Table 41.

TCR field descriptions (continued)

Bits

Name

Description

Table 42.

Timer status register (TSR)

37 38

Field ENW WIS

WRS

DIS FIS

—

Reset

0b(00||WRS)_0000_0000_0000_0000_0000_0000_0000

R/W

Read/Clear

SPR

SPR 336

Table 43.

Timer status register field descriptions

Bits

Name

Description

ENW

Enable next watchdog time. When a watchdog timer time-out occurs while WIS = 0 and the next

watchdog time-out is enabled (ENW = 1), a watchdog timer exception is generated and logged by

setting WIS. This is a watchdog timer first time out. A watchdog timer interrupt occurs if enabled by

TCR[WIE] and MSR[CE]. To avoid another watchdog timer interrupt when MSR[CE] is reenabled

(assuming TCR[WIE] is not cleared instead), the interrupt handler must reset TSR[WIS] by

executing an mtspr, setting WIS and any other bits to be cleared and a 0 in all other bits. The data

written to the TSR is not direct data, but is a mask. A 1 causes the bit to be cleared; a 0 has no

effect.

0 Action on next watchdog timer time-out is to set TSR[ENW].

1 Action on next watchdog timer time-out is governed by TSR[WIS].

WIS

Watchdog timer interrupt status. See the ENW description for details on how WIS is used.

0 No watchdog timer event.

1 A watchdog timer event. When MSR[CE] = 1 and TCR[WIE] = 1, a watchdog timer

interrupt is taken.

34–35

WRS

Watchdog timer reset status.

00 No second time-out of watchdog timer.

01 Force processor checkstop on second time-out of watchdog timer.

10 Assert processor reset output (

p_resetout_b) on second time-out of watchdog timer.

11 Reserved.

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