UM0434 datasheet(72/390 Pages) STMICROELECTRONICS

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UM0434

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IAC4

Instruction address compare 4 debug event enable.

0 IAC4 debug events are disabled.

1 IAC4 debug events are enabled.

44–45

DAC1

Data address compare 1 debug event enable

00 DAC1 debug events are disabled.

01 DAC1 debug events are enabled only for store

-type data storage accesses.

10 DAC1 debug events are enabled only for load

-type data storage accesses.

11 DAC1 debug events are enabled for load

-type or store-type data storage accesses.

46–47

DAC2

Data address compare 2 debug event enable.

00 DAC2 debug events are disabled.

01 DAC2 debug events are enabled only for store

-type data storage accesses.

10 DAC2 debug events are enabled only for load

-type data storage accesses.

11 DAC2 debug events are enabled for load

-type or store-type data storage accesses.

RET

Return debug event enable.

0 RET debug events are disabled.

1 RET debug events are enabled.

49–52

—

Reserved.

DEVT1

External debug event 1 enable.

0 DEVT1 debug events are disabled.

1 DEVT1 debug events are enabled.

DEVT2

External debug event 2 enable.

0 DEVT2 debug events are disabled.

1 DEVT2 debug events are enabled.

DCNT1

Debug counter 1 debug event enable.

0 counter 1 debug events are disabled.

1 counter 1 debug events are enabled.

DCNT2

Debug counter 2 debug event enable.

0 counter 2 debug events are disabled.

1 counter 2 debug events are enabled.

CIRPT

Critical interrupt taken debug event enable.

0 CIRPT debug events are disabled.

1 CIRPT debug events are enabled.

CRET

Critical return debug event enable.

0 CRET debug events are disabled.

1 CRET debug events are enabled.

VLES

VLE status, Set if an ICMP, BRT, TRAP, RET, CRET, IAC, or DAC debug event occurred on a VLE

instruction. Undefined for IRPT, CIRPT, DEVT[1,2], DCNT[1,2], and UDE events.

60–62

—

Reserved.

Freeze timers on debug event.

0 Timebase timers are unaffected by set DBSR bits.

1 Disable clocking of timebase timers if any DBSR bit is set (except MRR or CNT1TRG).

Table 51.

DBCR0 field descriptions (continued)

Bits

Name

Description

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