UM0434 datasheet(24/390 Pages) STMICROELECTRONICS

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UM0434

e200z3 core complex overview

25/391

The e200z3 is a single-issue, 32-bit, Book E–compliant design with 64-bit, general-purpose

registers (GPRs).

A signal processing extension (SPE) APU and embedded vector and scalar floating-point

APUs are provided to support real-time integer and single-precision embedded floating-

point operations using the GPRs. The e200z3 does not support Book E floating-point

instructions in hardware but traps them so they can be emulated by software.

All arithmetic instructions that execute in the core operate on data in the GPRs, which have

been extended to 64 bits to support vector instructions defined by the SPE and embedded

vector floating-point APUs. These instructions operate on a vector pair of 16- or 32-bit data

types and deliver vector and scalar results.

The e200z3 contains a memory management unit (MMU) and a Nexus Class 3+ module.

The e200z3 platform is specified in such a way that functional units can be added or

removed. The e200z3 can be configured with a powerful vectored interrupt controller and

one or more IP slave interfaces, as well as support for configured memory units.

3.1.1

Features

Key features of the e200z3 are summarized as follows:

●

Single-issue, 32-bit Book E–compliant core

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Implementation of the VLE APU for reduced code footprint

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In-order execution and retirement

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Precise interrupt handling

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Branch processing unit (BPU)

–

Dedicated branch address calculation adder

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Branch target prefetching using an eight-entry branch target buffer (BTB)

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Branch acceleration using branch lookahead instruction buffer

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Load/store unit (LSU)

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31-cycle load latency

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Fully pipelined

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Big- and little-endian support on a per-page basis

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Misaligned access support

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Zero load-to-use pipeline bubbles

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Power management

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Low-power design—extensive clock gating

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Power-saving modes: doze, nap, sleep

–

Dynamic power management of execution units, caches, and MMUs

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AMBA™ (advanced microcontroller bus architecture) AHB (advanced high-

performance bus)-Lite 64-bit system bus

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MMU with 16-entry, fully associative TLB and multiple page-size support

●

Signal processing extension (SPE) APU supporting integer operations using both

halves of the 64-bit GPRs

●

Single-precision embedded scalar floating-point APU

●

Single-precision embedded vector floating-point APU that uses both halves of the 64-

bit GPRs

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