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UM0434 Datasheet(PDF) 1 Page - STMicroelectronics

Part # UM0434
Description  The primary objective of this user?셲 manual is to describe
PDF  390 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UM0434 Datasheet(HTML) 1 Page - STMicroelectronics

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UM0434
e200z3 PowerPC core
Reference manual
Introduction
The primary objective of this user’s manual is to describe the functionality of the e200z3
embedded microprocessor core for software and hardware developers. This book is
intended as a companion to the
EREF: A Programmer's Reference Manual for Freescale
Book E Processors (hereafter referred to as EREF).
Book E is a PowerPC™ architecture definition for embedded processors that ensures binary
compatibility with the user-instruction set architecture (UISA) portion of the PowerPC
architecture as it was jointly developed by Apple, IBM, and Motorola (referred to as the AIM
architecture).
This document distinguishes among the three levels of the architectural and implementation
definition, as follows:
●
The Book E architecture—Book E defines a set of user-level instructions and registers
that are drawn from the user instruction set architecture (UISA) portion of the AIM
definition PowerPC architecture. Book E also includes numerous supervisor-level
registers and instructions as they were defined in the AIM version of the PowerPC
architecture for the virtual environment architecture (VEA) and the operating
environment architecture (OEA).
Because the operating system resources (such as the MMU and interrupts) defined by
Book E differ greatly from those defined by the AIM architecture, Book E introduces
many new registers and instructions.
●
Freescale Book E implementation standards (EIS)—In many cases, the Book E
architecture definition provides a general framework, leaving specific details up to the
implementation. To ensure consistency among its Book E implementations, Freescale
has defined implementation standards that provide an additional layer of architecture
between Book E and the actual devices.
●
e200z3 implementation details—Each processor typically defines instructions,
registers, register fields, and other aspects that are more detailed than either the
Book E definition or the EIS. This book describes all of the instructions and registers
implemented on the e200z3, including those defined by Book E and by the EIS, as well
as those that are e200z3-specific.
Information in this book is subject to change without notice, as described in the disclaimers
on the title page of this book. As with any technical documentation, it is the readers’
responsibility to be sure they are using the most recent version of the documentation.
www.st.com


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