UM0434 datasheet(25/390 Pages) STMICROELECTRONICS

25 / 390 page

e200z3 core complex overview

UM0434

26/391

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Nexus Class 3+ real-time development unit

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e200z3-specific debug interrupt. The e200z3 implements the debug interrupt as

defined in Book E with the following changes:

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When the debug APU is enabled (HID0[DAPUEN] = 1), debug is no longer a

critical interrupt, but uses DSRR0 and DSRR1 for saving machine state on context

switch.

–

The Return from Debug Interrupt (rfdi) instruction supports the debug APU

save/restore registers (DSRR0 and DSRR1).

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A critical interrupt taken debug event allows critical interrupts to generate a debug

event.

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A critical interrupt return debug event allows debug events to be generated for rfci

instructions. Testability

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Synthesizable, full MuxD scan design

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ABIST/MBIST for optional memory arrays

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Testability

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Synthesizable, full MuxD scan design

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ABIST/MBIST for optional memory arrays

3.2

Programming model

This section describes the register model, instruction model, and the interrupt model as they

are defined by Book E, EIS, and the e200z3 implementation.

3.2.1

Figure 2 shows the e200z3 register set, indicating which registers are accessible in

supervisor mode and which are accessible in user mode. The number to the left of the

special-purpose registers (SPRs) is the decimal number used in the instruction syntax to

access the register. (For example, the integer exception register (XER) is SPR 1.)

GPRs are accessed through instruction operands. Access to other registers can be explicit

(by using instructions for that purpose such as the Move To Special Purpose Register

(mtspr) and Move From Special Purpose Register (mfspr) instructions) or implicit as part of

the execution of an instruction. Some registers are accessed both explicitly and implicitly.

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