UM0434 datasheet(76/390 Pages) STMICROELECTRONICS

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UM0434

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Debug control register 3 (DBCR3)

DBCR3, shown in

Table 55, is an e200z3 implementation-specific register to enable and

configure the debug counter and debug counter events. For counter operation, the specific

debug events that cause counters to decrement are specified in DBCR3.

Note:

Corresponding events do not need to be (and probably should not be) enabled in DBCR0.

The IAC1–IAC4 and DAC1–DAC2 control fields in DBCR0 are ignored for counter

operations and the control fields in DBCR3 determine when counting is enabled. DBCR1

and DBCR2 control fields are also used to determine the configuration of IAC1–IAC4 and

DAC1–DAC2 operations for counting, even though the setting of bits in DBSR by

corresponding events can be disabled via DBCR0. Multiple count-enabled events that occur

during execution of an instruction typically cause only one decrement of a counter. For

example, if more than one IAC or DAC register hits and is enabled for counting, only one

count can occur per counter. During execution of lmw and stmw instructions, multiple DAC

hits can occur. If the instruction is not interrupted before completion, a single decrement of a

counter occurs.

38–39

DAC2ER

Data address compare 2 effective/real mode.

00 DAC2 debug events are based on effective address.

01 Unimplemented in the e200z3 (Book E real address compare), no match can occur.

10 DAC2 debug events are based on effective address and can occur only if MSR[DS] = 0.

11 DAC2 debug events are based on effective address and can occur only if MSR[DS] = 1.

40–41

DAC12M

Data address compare 1/2 mode.

00 Exact address compare. DAC1 debug events can occur only if the address of the data

access is equal to the value specified in DAC1. DAC2 debug events can occur only if the

address of the data access is equal to the value specified in DAC2.

01 Address bit match. DAC1 debug events can occur only if the address of the data access

ANDed with the contents of DAC2 is equal to the contents of DAC1, also ANDed with the

contents of DAC2. DAC2 debug events do not occur. DAC1US and DAC1ER settings are used.

10 Inclusive address range compare. DAC1 debug events can occur only if the address of the

data access is greater than or equal to the value specified in DAC1 and less than the value

specified in DAC2. DAC2 debug events do not occur. DAC1US and DAC1ER settings are used.

11 Exclusive address range compare. DAC1 debug events can occur only if the address of the

data access is less than the value specified in DAC1 or is greater than or equal to the value

specified in DAC2. DAC2 debug events do not occur. DAC1US and DAC1ER settings are used.

DAC1LNK

Data address compare 1 linked.

0 No effect.

1 DAC1 debug events are linked to IAC1 debug events. IAC1 debug events do not affect DBSR.

When linked to IAC1, DAC1 debug events are conditioned based on whether the instruction

also generated an IAC1 debug event.

DAC2LNK

Data address compare 2 linked

0 No effect.

1DAC 2 debug events are linked to IAC3 debug events. IAC3 debug events do not affect DBSR.

When linked to IAC3, DAC2 debug events are conditioned based on whether the instruction

also generated an IAC3 debug event. DAC2 can only be linked if DAC12M specifies exact

address compare because DAC2 debug events are not generated in the other compare modes.

44–63

—

Reserved for data value compare control (not supported by the e200z3).

Table 54.

DBCR2 field descriptions (continued)

Bits

Name

Description

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