UM0434 datasheet(75/390 Pages) STMICROELECTRONICS

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UM0434

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Debug control register 2 (DBCR2)

DBCR2, shown below is used to configure data address compare operations.

Table 54 describes DBCR2 fields.

56–57 IAC34M

Instruction address compare 3/4 mode.

00 Exact address compare. IAC3 debug events can occur only if the address of the instruction

fetch is equal to the value specified in IAC3. IAC4 debug events can occur only if the address of

the instruction fetch is equal to the value specified in IAC4.

01 Address bit match. IAC3 debug events can occur only if the address of the instruction fetch

ANDed with the contents of IAC4 is equal to the contents of IAC3, also ANDed with the contents

of IAC4. IAC4 debug events do not occur. IAC3US and IAC3ER settings are used.

10 Inclusive address range compare. IAC3 debug events can occur only if the address of the

instruction fetch is greater than or equal to the value specified in IAC3 and less than the value

specified in IAC4. IAC4 debug events do not occur. IAC3US and IAC3ER settings are used.

11 Exclusive address range compare. IAC3 debug events can occur only if the address of the

instruction fetch is less than the value specified in IAC3 or is greater than or equal to the value

specified in IAC4. IAC4 debug events do not occur. IAC3US and IAC3ER settings are used.

58–63

—

Reserved

Table 53.

DBCR1 field descriptions (continued)

Bits

Name

Description

Field

DAC1US

DAC1ER

DAC2US

DAC2ER

DAC12M

DAC1LNK

DAC2LNK

—

Reset

All zeros

R/W

SPR

SPR 310

Table 54.

DBCR2 field descriptions

Bits

Name

Description

32–33

DAC1US

Data address compare 1 user/supervisor mode.

00 DAC1 debug events are not affected by MSR[PR].

01 Reserved.

10 DAC1 debug events can occur only if MSR[PR] = 0 (supervisor mode).

11 DAC1 debug events can occur only if MSR[PR] = 1 (User mode).

34–35

DAC1ER

Data address compare 1 effective/real mode.

00 DAC1 debug events are based on effective address.

01 Unimplemented in the e200z3 (Book E real address compare), no match can occur.

10 DAC1 debug events are based on effective address and can occur only if MSR[DS] = 0.

11 DAC1 debug events are based on effective address and can occur only if MSR[DS] = 1.

36–37

DAC2US

Data Address compare 2 user/supervisor mode.

00 DAC2 debug events are not affected by MSR[PR].

01 Reserved

10 DAC2 debug events can occur only if MSR[PR] = 0 (supervisor mode).

11 DAC2 debug events can occur only if MSR[PR] = 1 (user mode).

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