UM0434 datasheet(41/390 Pages) STMICROELECTRONICS

41 / 390 page

UM0434

42/391

4.2

e200z3 - Specific registers

Book E allows implementation-specific registers. Those in the e200z3 core are as follows:

●

User-level registers, which are accessible to all software with either user or supervisor

privileges:

–

Signal processing/embedded floating-point status and control register

(SPEFSCR). Contains all integer and floating-point exception signal bits,

exception summary bits, exception enable bits, and rounding control bits for

compliance with the IEEE 754 standard.

–

L1 cache configuration register (L1CFG0). A read-only register that allows

software to query the configuration of the L1 cache. For the e200z3, this register

returns all zeros.

–

The EIS-defined accumulator, which is part of the SPE APU. See

Section 4.7.2:

Accumulator (ACC) on page 55.”

●

Supervisor-level registers, which are defined in the e200z3 in addition to the Book E

registers described in

Section 4.1: PowerPC Book E registers on page 39:

–

Configuration registers—Hardware implementation-dependent registers 0 and 1

(HID0 and HID1). Control various processor and system functions.

–

Exception handling and control registers:

–

Machine check syndrome register (MCSR). A syndrome to differentiate

between the different kinds of conditions that can generate a machine check.

–

Debug save/restore register 0 (DSRR0). When the debug APU is enabled,

DSRR0 saves the address of the instruction at which execution continues

when rfdi executes at the end of a debug interrupt handler routine.

–

Debug save/restore register 1 (DSRR1). When the debug APU is enabled,

(HID0[DAPUEN] = 1), DSRR1 saves machine state from the MSR on debug

interrupts and restores machine state when rfdi executes.

–

Debug facility registers

–

Debug control register 3 (DBCR3). Control for debug functions not described

in Book E

–

Debug counter register (DBCNT). Counter capability for debug functions

–

Context control registers

–

Context control register (CTXCR). Control for register context selection.

–

Branch unit control and status register (BUCSR). Controls operation of the branch

target buffer (BTB).

–

Cache registers. This e200z3-specific register may not be supported by other

PowerPC processors.

–

L1 cache configuration register (L1CFG0). A read-only register that allows

software to query the configuration of the L1 cache. This register returns all

zeros for e200z3 core.

–

Memory management unit (MMU) registers:

–

MMU configuration register (MMUCFG). A read-only register that allows

software to query the configuration of the MMU.

–

MMU assist (MAS0–MAS4, MAS6) registers. The interface to the e200z3

core from the MMU.

–

MMU control and status register (MMUCSR0). Controls MMU invalidation.

UM0434 Datasheet(PDF) 41 Page - STMicroelectronics

UM0434 Datasheet(HTML) 41 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL