UM0434 datasheet(119/390 Pages) STMICROELECTRONICS

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Instruction model

UM0434

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5.10.4

Embedded vector and scalar single precision floating point APU

instructions

The vector and scalar SPFP APUs perform floating-point operations on single-precision

operands. These operations are IEEE-compliant with software interrupt handlers and offer a

simpler interrupt model than the floating-point instructions defined by the PowerPC ISA.

Instead of FPRs, these instructions use GPRs and offer improved performance for

Vector Shift Left Word Immediate

evslwi

rD,rA,UIMM

Vector Shift Right Word Immediate Signed

evsrwis

rD,rA,UIMM

Vector Shift Right Word Immediate Unsigned

evsrwiu

rD,rA,UIMM

Vector Shift Right Word Signed

evsrws

rD,rA,rB

Vector Shift Right Word Unsigned

evsrwu

rD,rA,rB

Vector Splat Fractional Immediate

evsplatfi

rD,SIMM

Vector Splat Immediate

evsplati

rD,SIMM

Vector Store Double of Double

evstdd

rS,d(rA)

Vector Store Double of Double Indexed

evstddx

rS,rA,rB

Vector Store Double of Four Half Words

evstdh

rS,d(rA)

Vector Store Double of Four Half Words Indexed

evstdhx

rS,rA,rB

Vector Store Double of Two Words

evstdw

rS,d(rA)

Vector Store Double of Two Words Indexed

evstdwx

rS,rA,rB

Vector Store Word of Two Half Words from Even

evstwhe

rS,d(rA)

Vector Store Word of Two Half Words from Even Indexed

evstwhex

rS,rA,rB

Vector Store Word of Two Half Words from Odd

evstwho

rS,d(rA)

Vector Store Word of Two Half Words from Odd Indexed

evstwhox

rS,rA,rB

Vector Store Word of Word from Even

evstwwe

rS,d(rA)

Vector Store Word of Word from Even Indexed

evstwwex

rS,rA,rB

Vector Store Word of Word from Odd

evstwwo

rS,d(rA)

Vector Store Word of Word from Odd Indexed

evstwwox

rS,rA,rB

Vector Subtract from Word

evsubfw

rD,rA,rB

Vector Subtract Immediate from Word

evsubifw

rD,UIMM,rB

Vector Subtract Signed, Modulo, Integer to Accumulator Word

evsubfsmiaaw

rD,rA

Vector Subtract Signed, Saturate, Integer to Accumulator Word

evsubfssiaaw

rD,rA

Vector Subtract Unsigned, Modulo, Integer to Accumulator Word

evsubfumiaaw

rD,rA

Vector Subtract Unsigned, Saturate, Integer to Accumulator Word

evsubfusiaaw

rD,rA

Vector XOR

evxor

rD,rA,rB

An implementation can restrict the number of bits specified in a mask. The e200z3 limits it to 16 bits, which allows the user

to perform bit-reversed address computations for 65536-byte samples.

Table 106.

SPE APU vector instructions (continued)

Instruction

Mnemonic

Syntax

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