R5F72115D160FPV datasheet(334/1228 Pages) RENESAS

334 / 1228 page

Section 9 Direct Memory Access Controller (DMAC)

Rev. 2.00 May. 08, 2008 Page 310 of 1200

REJ09B0344-0200

9.3.4

DMA Channel Control Registers (CHCR)

The DMA channel control registers (CHCR) are 32-bit readable/writable registers that control

DMA transfer mode.

The DO, AM, AL, DL, and DS bits which specify the DREQ and DACK external pin functions

can be read and written to in channels 0 to 3, but they are reserved in channels 4 to 7. The TL bit

which specifies the TEND external pin function can be read and written to in channels 0 and 1, but

it is reserved in channels 2 to 7.

CHCR is initialized to H'00000000 by a reset and retains the value in software standby mode and

module standby mode.

0000000000000000

R/W

R/(W)* R/W

R/W

0000000000000000

R/W

R/W R/(W)* R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

Note:

Only 0 can be written to clear the flag after 1 is read.

RLD

HIE

DM[1:0]

SM[1:0]

RS[3:0]

TS[1:0]

Bit

Bit Name

Initial

Value

R/W

Descriptions

R/W

Transfer Count Mode

Specifies whether to transmit data once or for the

count specified in DMATCR by one transfer request.

Note that when this bit is set to 0, the TB bit must not

be set to 1 (burst mode). When the SCIF or IIC3 is

selected for the transfer request source, this bit (TC)

must not be set to 1.

0: Transmits data once by one transfer request

1: Transmits data for the count specified in DMATCR

by one transfer request

30, 29

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

R5F72115D160FPV Datasheet(PDF) 334 Page - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 334 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL