R5F72115D160FPV datasheet(369/1228 Pages) RENESAS

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Section 9 Direct Memory Access Controller (DMAC)

Rev. 2.00 May. 08, 2008 Page 345 of 1200

REJ09B0344-0200

9.4.5

Number of Bus Cycles and DREQ Pin Sampling Timing

(1)

Number of Bus Cycles

When the DMAC is the bus master, the number of bus cycles is controlled by the bus state

controller (BSC) in the same way as when the CPU is the bus master. For details, see section 8,

Bus State Controller (BSC).

(2)

DREQ Pin Sampling Timing

Figures 9.13 to 9.16 show the DREQ input sampling timings in each bus mode.

DREQ

DACK

Bus cycle

(Rising)

(Active-high)

1st acceptance

2nd acceptance

CPU

Acceptance start

DMAC

Non sensitive period

Figure 9.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection

DREQ

(Overrun 0 at

high level)

DACK

(Active-high)

Bus cycle

1st acceptance

CPU

DMAC

DREQ

(Overrun 1 at

high level)

DACK

(Active-high)

Bus cycle

2nd acceptance

CPU

DMAC

Acceptance

start

Acceptance

start

2nd acceptance

1st acceptance

Non sensitive period

Figure 9.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection

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