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R5F72115D160FPV Datasheet(PDF) 372 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 372 Page - Renesas Technology Corp |
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372 / 1228 page ![]() Section 9 Direct Memory Access Controller (DMAC) Rev. 2.00 May. 08, 2008 Page 348 of 1200 REJ09B0344-0200 CK Address RD Data WEn WAIT CS T1 T2 Taw T1 T2 DACKn (Active low) TEND (Active low) Note: TEND is asserted for the last unit of DMA transfer. If a transfer unit is divided into multiple bus cycles and the CS is negated between the bus cycles, TEND is also divided. Figure 9.18 BSC Normal Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device) |
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