R5F72115D160FPV datasheet(191/1228 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 May. 08, 2008 Page 167 of 1200

REJ09B0344-0200

⎯ I bus cycles (including read fill cycles) resulting from instruction fetches on the C bus by

the CPU are defined as instruction fetch cycles on the I bus, while other bus cycles are

defined as data access cycles.

⎯ The DMAC only issues data access cycles for I bus cycles.

⎯ If a break condition is specified for the I bus, even when the condition matches in an I bus

cycle resulting from an instruction executed by the CPU, at which instruction the user

break is to be accepted cannot be clearly defined.

7.4.2

Break on Instruction Fetch Cycle

1. When C bus/instruction fetch/read/word or longword is set in the break bus cycle register

(BBR), the break condition is the FAB bus instruction fetch cycle. Whether PC breaks are set

before or after the execution of the instruction can then be selected with the PCB0 or PCB1 bit

of the break control register (BRCR) for the appropriate channel. If an instruction fetch cycle is

set as a break condition, clear LSB in the break address register (BAR) to 0. A break cannot be

generated as long as this bit is set to 1.

2. A break for instruction fetch which is set as a break before instruction execution occurs when it

is confirmed that the instruction has been fetched and will be executed. This means a break

does not occur for instructions fetched by overrun (instructions fetched at a branch or during

an interrupt transition, but not to be executed). When this kind of break is set for the delay slot

of a delayed branch instruction, the break is not generated until the execution of the first

instruction at the branch destination.

Note:

If a branch does not occur at a delayed branch instruction, the subsequent instruction is

not recognized as a delay slot.

3. When setting a break condition for break after instruction execution, the instruction set with

the break condition is executed and then the break is generated prior to execution of the next

instruction. As with pre-execution breaks, a break does not occur with overrun fetch

instructions. When this kind of break is set for a delayed branch instruction and its delay slot,

the break is not generated until the first instruction at the branch destination.

4. When an instruction fetch cycle is set, the break data register (BDR) is ignored. Therefore,

break data cannot be set for the break of the instruction fetch cycle.

5. If the I bus is set for a break of an instruction fetch cycle, the setting is invalidated.

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