R5F72115D160FPV datasheet(187/1228 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 May. 08, 2008 Page 163 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

SCMFC0

R/W

C Bus Cycle Condition Match Flag 0

When the C bus cycle condition in the break conditions

set for channel 0 is satisfied, this flag is set to 1. In

order to clear this flag, write 0 to this bit.

0: The C bus cycle condition for channel 0 does not

match

1: The C bus cycle condition for channel 0 matches

SCMFC1

R/W

C Bus Cycle Condition Match Flag 1

When the C bus cycle condition in the break conditions

set for channel 1 is satisfied, this flag is set to 1. In

order to clear this flag, write 0 to this bit.

0: The C bus cycle condition for channel 1 does not

match

1: The C bus cycle condition for channel 1 matches

SCMFC2

R/W

C Bus Cycle Condition Match Flag 2

When the C bus cycle condition in the break conditions

set for channel 2 is satisfied, this flag is set to 1. In

order to clear this flag, write 0 to this bit.

0: The C bus cycle condition for channel 2 does not

match

1: The C bus cycle condition for channel 2 matches

SCMFC3

R/W

C Bus Cycle Condition Match Flag 3

When the C bus cycle condition in the break conditions

set for channel 3 is satisfied, this flag is set to 1. In

order to clear this flag, write 0 to this bit.

0: The C bus cycle condition for channel 3 does not

match

1: The C bus cycle condition for channel 3 matches

SCMFD0

R/W

I Bus Cycle Condition Match Flag 0

When the I bus cycle condition in the break conditions

set for channel 0 is satisfied, this flag is set to 1. In

order to clear this flag, write 0 to this bit.

0: The I bus cycle condition for channel 0 does not

match

1: The I bus cycle condition for channel 0 matches

R5F72115D160FPV Datasheet(PDF) 187 Page - Renesas Technology Corp

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