R5F72115D160FPV datasheet(309/1228 Pages) RENESAS

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 285 of 1200

REJ09B0344-0200

8.5.9

Burst ROM (Clock Synchronous) Interface

The burst ROM (clock synchronous) interface is supported to access a ROM with a synchronous

burst function at high speed. The burst ROM interface accesses the burst ROM in the same way as

a normal space. This interface is valid only for area 0.

In the first access cycle, wait cycles are inserted. In this case, the number of wait cycles to be

inserted is specified by the W3 to W0 bits in CS0WCR. In the second and subsequent cycles, the

number of wait cycles to be inserted is specified by the BW1 and BW0 bits in CS0WCR.

While the burst ROM (clock synchronous) is accessed, the

BS signal is asserted only for the first

access cycle and an external wait input is also valid for the first access cycle.

If the bus width is 16 bits, the burst length must be specified as 8. The burst ROM interface does

not support the 8-bit bus width for the burst ROM.

The burst ROM interface performs burst operations for all read access. For example, in a

longword access over a 16-bit bus, valid 16-bit data is read two times and invalid 16-bit data is

read six times. These invalid data read cycles increase the memory access time and degrade the

program execution speed and DMA transfer speed. To prevent this problem, using 16-byte read by

the DMA is recommended. The burst ROM interface performs write access in the same way as

normal space access.

Twb

T2B

Twb

T2B

Twb

T2B

Twb

T2B

Twb

Note: * The waveform for DACKn is when active low is specified.

CS0

RD/

A25 to A0

D15 to D0

WAIT

DACKn*

Figure 8.37 Burst ROM Access Timing (Clock Synchronous)

(Burst Length = 8, Wait Cycles Inserted in First Access = 2,

Wait Cycles Inserted in Second and Subsequent Access Cycles = 1)

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