R5F72115D160FPV datasheet(312/1228 Pages) RENESAS

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 288 of 1200

REJ09B0344-0200

No. Condition

Description

Range

Note

(5)

Read data

transfer cycle

One idle cycle is inserted after a

read access is completed. This idle

cycle is not generated for the first or

middle cycles in divided access

cycles. This is neither generated

when the HM[1:0] bits in CSnWCR

are not B'00.

0 or 1

One idle cycle is always

generated after a read cycle

with SDRAM interface.

(6)

Internal bus

idle cycles, etc.

External bus access requests from

the CPU or DMAC and their results

are passed through the internal

bus. The external bus enters idle

state during internal bus idle cycles

or while a bus other than the

external bus is being accessed.

This condition is not effective for

divided access cycles, which are

generated by the BSC when the

access size is larger than the

external data bus width.

0 or

larger

The number of internal bus

idle cycles may not become 0

depending on the I

φ:Bφ clock

ratio. Tables 8.17 and 8.18

show the relationship

between the clock ratio and

the minimum number of

internal bus idle cycles.

(7)

Write data wait

cycles

During write access, a write cycle is

executed on the external bus only

after the write data becomes ready.

This write data wait period

generates idle cycles before the

write cycle. Note that when the

previous cycle is a write cycle and

the internal bus idle cycles are

shorter than the previous write

cycle, write data can be prepared in

parallel with the previous write cycle

and therefore, no idle cycle is

generated (write buffer effect).

0 or 1

For write

→ write or write →

read access cycles,

successive access cycles

without idle cycles are

frequently available due to

the write buffer effect

described in the left column. If

successive access cycles

without idle cycles are not

allowed, specify the minimum

number of idle cycles

between access cycles

through CSnBCR.

(8)

Idle cycles

between

different

memory types

To ensure the minimum pulse width

on the signal-multiplexed pins, idle

cycles may be inserted before

access after memory types are

switched. For some memory types,

idle cycles are inserted even when

memory types are not switched.

0 to 2.5 The number of idle cycles

depends on the target

memory types. See table

8.19.

R5F72115D160FPV Datasheet(PDF) 312 Page - Renesas Technology Corp

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