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EP4CE40 Datasheet(PDF) 103 Page - Altera Corporation |
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EP4CE40 Datasheet(HTML) 103 Page - Altera Corporation |
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103 / 488 page ![]() Chapter 5: Clock Networks and PLLs in Cyclone IV Devices 5–41 Spread-Spectrum Clocking October 2012 Altera Corporation Cyclone IV Device Handbook, Volume 1 Figure 5–26 shows the dynamic phase shifting waveform. The PHASESTEP signal is latched on the negative edge of SCANCLK (a,c) and must remain asserted for at least two SCANCLK cycles. Deassert PHASESTEP after PHASEDONE goes low. On the second SCANCLK rising edge (b,d) after PHASESTEP is latched, the values of PHASEUPDOWN and PHASECOUNTERSELECT are latched and the PLL starts dynamic phase-shifting for the specified counters, and in the indicated direction. PHASEDONE is deasserted synchronous to SCANCLK at the second rising edge (b,d) and remains low until the PLL finishes dynamic phase-shifting. Depending on the VCO and SCANCLK frequencies, PHASEDONE low time may be greater than or less than one SCANCLK cycle. You can perform another dynamic phase-shift after the PHASEDONE signal goes from low to high. Each PHASESTEP pulse enables one phase shift. PHASESTEP pulses must be at least one SCANCLK cycle apart. f For information about the ALTPLL_RECONFIG MegaWizard™ Plug-In Manager, refer to the ALTPLL_RECONFIG Megafunction User Guide. Spread-Spectrum Clocking Cyclone IV devices can accept a spread-spectrum input with typical modulation frequencies. However, the device cannot automatically detect that the input is a spread-spectrum signal. Instead, the input signal looks like deterministic jitter at the input of the PLL. PLLs of Cyclone IV devices can track a spread-spectrum input clock as long as it is in the input jitter tolerance specifications and the modulation frequency of the input clock is below the PLL bandwidth, that is specified in the fitter report. Cyclone IV devices cannot generate spread-spectrum signals internally. PLL Specifications f For information about PLL specifications, refer to the Cyclone IV Device Datasheet chapter. Figure 5–26. PLL Dynamic Phase Shift PHASEDONE goes low synchronous with SCANCLK SCANCLK PHASESTEP PHASEUPDOWN PHASECOUNTERSELECT PHASEDONE a b c d |
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