EP4CE40 datasheet(108/488 Pages) ALTERA

108 / 488 page

6–2

Chapter 6: I/O Features in Cyclone IV Devices

Cyclone IV I/O Elements

Cyclone IV Device Handbook,

May 2013

Altera Corporation

Volume 1

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“Pad Placement and DC Guidelines” on page 6–23

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“Clock Pins Functionality” on page 6–23

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“High-Speed I/O Interface” on page 6–24

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“High-Speed I/O Standards Support” on page 6–28

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“True Differential Output Buffer Feature” on page 6–35

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“High-Speed I/O Timing” on page 6–36

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“Design Guidelines” on page 6–37

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“Software Overview” on page 6–38

Cyclone IV I/O Elements

Cyclone IV I/O elements (IOEs) contain a bidirectional I/O buffer and five registers

for registering input, output, output-enable signals, and complete embedded

bidirectional single-data rate transfer. I/O pins support various single-ended and

differential I/O standards.

The IOE contains one input register, two output registers, and two output-enable (OE)

registers. The two output registers and two OE registers are used for DDR

applications. You can use input registers for fast setup times and output registers for

fast clock-to-output times. Additionally, you can use OE registers for fast

clock-to-output enable timing. You can use IOEs for input, output, or bidirectional

data paths.

EP4CE40 Datasheet(PDF) 108 Page - Altera Corporation