EP4CE40 datasheet(110/488 Pages) ALTERA

110 / 488 page

6–4

Chapter 6: I/O Features in Cyclone IV Devices

I/O Element Features

Cyclone IV Device Handbook,

May 2013

Altera Corporation

Volume 1

Table 6–2 on page 6–7 shows the possible settings for I/O standards with current

strength control. These programmable current strength settings are a valuable tool in

helping decrease the effects of simultaneously switching outputs (SSO) in conjunction

with reducing system noise. The supported settings ensure that the device driver

meets the specifications for IOH and IOL of the corresponding I/O standard.

1 When you use programmable current strength, on-chip series termination (R

S OCT) is

not available.

Slew Rate Control

The output buffer for each Cyclone IV I/O pin provides optional programmable

output slew-rate control. Table 6–2 on page 6–7 shows the possible slew rate option

and the Quartus II default slew rate setting. However, these fast transitions may

introduce noise transients in the system. A slower slew rate reduces system noise, but

adds a nominal delay to rising and falling edges. Because each I/O pin has an

individual slew-rate control, you can specify the slew rate on a pin-by-pin basis. The

slew-rate control affects both the rising and falling edges. Slew rate control is available

for single-ended I/O standards with current strength of 8 mA or higher.

1 You cannot use the programmable slew rate feature when using OCT with calibration.

1 You cannot use the programmable slew rate feature when using the 3.0-V PCI,

3.0-V PCI-X, 3.3-V LVTTL, or 3.3-V LVCMOS I/O standards. Only the fast slew rate

(default) setting is available.

Open-Drain Output

Cyclone IV devices provide an optional open-drain (equivalent to an open-collector)

output for each I/O pin. This open-drain output enables the device to provide

system-level control signals (for example, interrupt and write enable signals) that are

asserted by multiple devices in your system.

Bus Hold

Each Cyclone IV device user I/O pin provides an optional bus-hold feature. The

bus-hold circuitry holds the signal on an I/O pin at its last-driven state. Because the

bus-hold feature holds the last-driven state of the pin until the next input signal is

present, an external pull-up or pull-down resistor is not necessary to hold a signal

level when the bus is tri-stated.

The bus-hold circuitry also pulls undriven pins away from the input threshold

voltage in which noise can cause unintended high-frequency switching. You can select

this feature individually for each I/O pin. The bus-hold output drives no higher than

VCCIO to prevent overdriving signals.

1 If you enable the bus-hold feature, the device cannot use the programmable pull-up

option. Disable the bus-hold feature when the I/O pin is configured for differential

signals. Bus-hold circuitry is not available on dedicated clock pins.

Bus-hold circuitry is only active after configuration. When going into user mode, the

bus-hold circuit captures the value on the pin present at the end of configuration.

EP4CE40 Datasheet(PDF) 110 Page - Altera Corporation

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