R5F72115D160FPV datasheet(340/1228 Pages) RENESAS

340 / 1228 page

Section 9 Direct Memory Access Controller (DMAC)

Rev. 2.00 May. 08, 2008 Page 316 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Descriptions

R/W

DREQ Level

DREQ Edge Select

These bits specify the sampling method of the DREQ

pin input and the sampling level.

These bits are valid only in CHCR_0 to CHCR_3.

These bits are reserved in CHCR_4 to CHCR_7; they

are always read as 0 and the write value should

always be 0.

If the transfer request source is specified as an on-chip

peripheral module or if an auto-request is specified, the

specification by these bits is ignored.

00: DREQ detected in low level

01: DREQ detected at falling edge

10: DREQ detected in high level

11: DREQ detected at rising edge

R/W

Transfer Bus Mode

Specifies bus mode when DMA transfers data. Note

that burst mode must not be selected when TC = 0.

0: Cycle steal mode

1: Burst mode

4, 3

TS[1:0]

R/W

Transfer Size

These bits specify the size of data to be transferred.

Select the size of data to be transferred when the

source or destination is an on-chip peripheral module

00: Byte unit

01: Word unit (two bytes)

10: Longword unit (four bytes)

11: 16-byte unit (four longwords)

R/W

Interrupt Enable

Specifies whether or not an interrupt request is

generated to the CPU at the end of the DMA transfer.

Setting this bit to 1 generates an interrupt request

(DEI) to the CPU when TE bit is set to 1.

0: Disables an interrupt request

1: Enables an interrupt request

R5F72115D160FPV Datasheet(PDF) 340 Page - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 340 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL