R5F72115D160FPV datasheet(341/1228 Pages) RENESAS

341 / 1228 page

Section 9 Direct Memory Access Controller (DMAC)

Rev. 2.00 May. 08, 2008 Page 317 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Descriptions

R/(W)* Transfer End Flag

This bit is set to 1 when DMATCR becomes 0 and

DMA transfer ends.

The TE bit is not set to 1 in the following cases.

• DMA transfer ends due to an NMI interrupt or

DMA address error before DMATCR becomes 0.

• DMA transfer is ended by clearing the DE bit and

DME bit in DMA operation register (DMAOR).

To clear the TE bit, write 0 after reading TE = 1.

Even if the DE bit is set to 1 while this bit is set to 1,

transfer is not enabled.

0: During the DMA transfer or DMA transfer has been

terminated

[Clearing condition]

• Writing 0 after reading TE = 1

1: DMA transfer ends by the specified count

(DMATCR = 0)

R/W

DMA Enable

Enables or disables the DMA transfer. In auto-request

mode, DMA transfer starts by setting the DE bit and

DME bit in DMAOR to 1. In this case, all of the bits

TE, NMIF in DMAOR, and AE must be 0. In an

external request or peripheral module request, DMA

transfer starts if DMA transfer request is generated by

the devices or peripheral modules after setting the

bits DE and DME to 1. In this case, however, all of the

bits TE, NMIF, and AE must be 0 as in the case of

auto-request mode. Clearing the DE bit to 0 can

terminate the DMA transfer.

0: DMA transfer disabled

1: DMA transfer enabled

Note:

Only 0 can be written to clear the flag after 1 is read.

R5F72115D160FPV Datasheet(PDF) 341 Page - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 341 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL