R5F72115D160FPV datasheet(391/1228 Pages) RENESAS

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Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 May. 08, 2008 Page 367 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

BFB

R/W

Buffer Operation B

Specifies whether TGRB is to operate in the normal

way, or TGRB and TGRD are to be used together for

buffer operation. When TGRD is used as a buffer

generated in a mode other than complementary PWM.

TGRD compare match is generated in complementary

PWM mode. When compare match occurs during the

Tb period in complementary PWM mode, TGFD is set.

Therefore, set the TGIED bit in the timer interrupt

enable register 3/4 (TIER_3/4) to 0.

In channels 1 and 2, which have no TGRD, bit 5 is

reserved. It is always read as 0 and cannot be modified.

0: TGRB and TGRD operate normally

1: TGRB and TGRD used together for buffer operation

BFA

R/W

Buffer Operation A

Specifies whether TGRA is to operate in the normal

way, or TGRA and TGRC are to be used together for

buffer operation. When TGRC is used as a buffer

generated in a mode other than complementary PWM.

TGRC compare match is generated when in

complementary PWM mode. When compare match for

channel 4 occurs during the Tb period in

complementary PWM mode, TGFC is set. Therefore,

set the TGIEC bit in the timer interrupt enable register 4

(TIER_4) to 0.

In channels 1 and 2, which have no TGRC, bit 4 is

reserved. It is always read as 0 and cannot be modified.

0: TGRA and TGRC operate normally

1: TGRA and TGRC used together for buffer operation

3 to 0

MD[3:0]

0000

R/W

Modes 0 to 3

These bits are used to set the timer operating mode.

See table 10.11 for details.

R5F72115D160FPV Datasheet(PDF) 391 Page - Renesas Technology Corp

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