R5F72115D160FPV datasheet(393/1228 Pages) RENESAS

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Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 May. 08, 2008 Page 369 of 1200

REJ09B0344-0200

10.3.3

Timer I/O Control Register (TIOR)

The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU2

has a total of eleven TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 and

2, and three (TIORU_5, TIORV_5, and TIORW_5) for channel 5.

TIOR should be set while TMDR is set in normal operation, PWM mode, or phase counting mode.

The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is

cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is

cleared to 0 is specified.

When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register

operates as a buffer register.

• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4

Bit:

Initial value:

R/W:

7654321

00000000

R/W

IOB[3:0]

IOA[3:0]

Bit

Bit Name

Initial

Value

R/W

Description

7 to 4

IOB[3:0]

0000

R/W

I/O Control B0 to B3

Specify the function of TGRB.

See the following tables.

TIORH_0: Table 10.12

TIOR_1:

Table 10.14

TIOR_2:

Table 10.15

TIORH_3: Table 10.16

TIORH_4: Table 10.18

3 to 0

IOA[3:0]

0000

R/W

I/O Control A0 to A3

Specify the function of TGRA.

See the following tables.

TIORH_0: Table 10.20

TIOR_1:

Table 10.22

TIOR_2:

Table 10.23

TIORH_3: Table 10.24

TIORH_4: Table 10.26

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