R5F72115D160FPV datasheet(112/1228 Pages) RENESAS

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Section 5 Exception Handling

Rev. 2.00 May. 08, 2008 Page 88 of 1200

REJ09B0344-0200

5.3.2

Address Error Exception Handling

When an address error occurs, the bus cycle in which the address error occurred ends*. When the

executing instruction then finishes, address error exception handling starts. The CPU operates as

follows:

1. The exception service routine start address which corresponds to the address error that

occurred is fetched from the exception handling vector table.

2. The status register (SR) is saved to the stack.

3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the last executed instruction.

4. After jumping to the address fetched from the exception handling vector table, program

execution starts. The jump that occurs is not a delayed branch.

Note: * This is the case in which an address error was caused by data read or write. When an

address error is caused by an instruction fetch, and if the bus cycle in which the address

error occurred does not end by step 3 above, the CPU restarts the address error

exception handling until the bus cycle ends.

R5F72115D160FPV Datasheet(PDF) 112 Page - Renesas Technology Corp