R5F72115D160FPV datasheet(110/1228 Pages) RENESAS

110 / 1228 page

Section 5 Exception Handling

Rev. 2.00 May. 08, 2008 Page 86 of 1200

REJ09B0344-0200

5.2.3

Manual Reset

(1)

Manual Reset by Means of

MRES Pin

When the

MRES pin is driven low, this LSI enters the manual reset state. To reset this LSI without

fail, the

MRES pin should be kept at the low level for at least 20-tcyc. In the manual reset state,

the CPU’s internal state is initialized, but all the on-chip peripheral module registers are not

initialized. In the manual reset state, manual reset exception handling starts when the

MRES pin is

first driven low for a fixed period and then returned to high. The CPU operates as follows:

1. The initial value (execution start address) of the program counter (PC) is fetched from the

exception handling vector table.

2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.

3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to

I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are

initialized. The BN bit in IBNR of the INTC is also initialized to 0.

4. The values fetched from the exception handling vector table are set in the PC and SP, and the

program begins executing.

(2)

Manual Reset Initiated by WDT

When a setting is made for a manual reset to be generated in the WDT’s watchdog timer mode,

and WTCNT of the WDT overflows, this LSI enters the manual reset state.

When manual reset exception processing is started by the WDT, the CPU operates in the same

way as when a manual reset was caused by the

MRES pin.

When a manual reset is generated, the bus cycle is retained, but if a manual reset occurs while the

bus is released or during DMAC burst transfer, manual reset exception handling will be deferred

until the CPU acquires the bus. However, if the interval from generation of the manual reset until

the end of the bus cycle is equal to or longer than the fixed internal manual reset interval cycles,

the internal manual reset source is ignored instead of being deferred, and manual reset exception

handling is not executed.

R5F72115D160FPV Datasheet(PDF) 110 Page - Renesas Technology Corp