R5F72115D160FPV datasheet(107/1228 Pages) RENESAS

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Section 5 Exception Handling

Rev. 2.00 May. 08, 2008 Page 83 of 1200

REJ09B0344-0200

5.2

Resets

5.2.1

Types of Reset

A reset is the highest-priority exception handling source. There are two kinds of reset, power-on

and manual. As shown in table 5.5, the CPU state is initialized in both a power-on reset and a

manual reset. On-chip peripheral module registers are initialized by a power-on reset, but not by a

manual reset.

Table 5.5

Exception Source Detection and Exception Handling Start Timing

Conditions for Transition to Reset State

Internal States

Type

RES or

MRES

H-UDI Command

WDT

Overflow

CPU

On-Chip

Peripheral

Modules, I/O Port

WRCSR of WDT,

FRQCR of CPG

Low

—

Initialized

High

H-UDI reset assert

command is set

—

Initialized

Power-on

reset

High

Command other

than H-UDI reset

assert is set

Power-on

reset

Initialized

Not initialized

Low

—

Initialized

Not initialized*

Not initialized

Manual

reset

High

—

Manual

reset

Initialized

Not initialized*

Not initialized

Note:

The BN bit in IBNR of the INTC is initialized.

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