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R5F72115D160FPV Datasheet(PDF) 109 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 109 Page - Renesas Technology Corp |
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109 / 1228 page  Section 5 Exception Handling Rev. 2.00 May. 08, 2008 Page 85 of 1200 REJ09B0344-0200 (3) Power-On Reset Initiated by WDT When a setting is made for a power-on reset to be generated in the WDT’s watchdog timer mode, and WTCNT of the WDT overflows, this LSI enters the power-on reset state. In this case, WRCSR of the WDT and FRQCR of the CPG are not initialized by the reset signal generated by the WDT. If a reset caused by the RES pin or the H-UDI reset assert command occurs simultaneously with a reset caused by WDT overflow, the reset caused by the RES pin or the H-UDI reset assert command has priority, and the WOVF bit in WRCSR is cleared to 0. When power-on reset exception processing is started by the WDT, the CPU operates in the same way as when a power- on reset was caused by the RES pin. |
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