R5F72115D160FPV datasheet(126/1228 Pages) RENESAS

126 / 1228 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 May. 08, 2008 Page 102 of 1200

REJ09B0344-0200

Figure 6.1 shows a block diagram of the INTC.

(Interrupt request)

UBC

H-UDI

DMAC

CMT

BSC

WDT

MTU2

MTU2S

POE2

ADC

IIC3

SCIF

WAVEIF

UBC:

H-UDI:

DMAC:

CMT:

BSC:

WDT:

MTU2:

MTU2S:

POE2:

ADC:

IIC3:

SCIF:

WAVEIF:

ICR0:

ICR1:

IRQRR:

IBCR:

IBNR:

IPR01, 02, 05 to 15:

Priority

identifier

Com-

parator

Interrupt

request

CPU

Bus

interface

Module bus

User break controller

User debugging interface

Direct memory access controller

Compare match timer

Bus state controller

Watchdog timer

Multi-function timer pulse unit 2

Multi-function timer pulse unit 2S

Port output enable 2

A/D converter

I2C bus interface 3

Serial communication interface with FIFO

WAVE interface

Interrupt control register 0

Interrupt control register 1

IRQ interrupt request register

Bank control register

Bank number register

Interrupt priority registers 01, 02,

05 to 15

[Legend]

I3 I2 I1 I0

IBCR

IPR01, IPR02,

IPR05 to IPR15

ICR0

IBNR

ICR1

IRQRR

IRQ7 to IRQ0

NMI

IRQOUT

IPR

CPU/

DMAC

interrupt

requests

identifier

Input control

INTC

Figure 6.1 Block Diagram of INTC

R5F72115D160FPV Datasheet(PDF) 126 Page - Renesas Technology Corp

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