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R5F72115D160FPV Datasheet(PDF) 130 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 130 Page - Renesas Technology Corp |
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130 / 1228 page ![]() Section 6 Interrupt Controller (INTC) Rev. 2.00 May. 08, 2008 Page 106 of 1200 REJ09B0344-0200 Register Name Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 Interrupt priority register 13 MTU5S (TGI5U, TGI5V, TGI5W) POE2 (OEI3) IIC3 Reserved Interrupt priority register 14 SCIF0 SCIF1 SCIF2 SCIF3 Interrupt priority register 15 WAVEIF Reserved Reserved Reserved As shown in table 6.3, by setting the 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) with values from H'0 (0000) to H'F (1111), the priority of each corresponding interrupt is set. Setting of H'0 means priority level 0 (the lowest level) and H'F means priority level 15 (the highest level). IPR01, IPR02, and IPR05 to IPR15 are initialized to H'0000 by a power-on reset. |
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