R5F72115D160FPV datasheet(138/1228 Pages) RENESAS

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Section 6 Interrupt Controller (INTC)

Rev. 2.00 May. 08, 2008 Page 114 of 1200

REJ09B0344-0200

6.4

Interrupt Sources

There are five types of interrupt sources: NMI, user break, H-UDI, IRQ, and on-chip peripheral

modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the highest. When

set to level 0, that interrupt is masked at all times.

6.4.1

NMI Interrupt

The NMI interrupt has a priority level of 16 and is accepted at all times. NMI interrupt requests

are edge-detected, and the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0)

selects whether the rising edge or falling edge is detected.

Though the priority level of the NMI interrupt is 16, the NMI interrupt exception handling sets the

interrupt mask level bits (I3 to I0) in the status register (SR) to level 15.

6.4.2

User Break Interrupt

A user break interrupt which occurs when a break condition set in the user break controller (UBC)

matches has a priority level of 15. The user break interrupt exception handling sets the I3 to I0 bits

in SR to level 15. For user break interrupts, see section 7, User Break Controller (UBC).

6.4.3

H-UDI Interrupt

The user debugging interface (H-UDI) interrupt has a priority level of 15, and occurs at serial

input of an H-UDI interrupt instruction. H-UDI interrupt requests are edge-detected and retained

until they are accepted. The H-UDI interrupt exception handling sets the I3 to I0 bits in SR to level

15. For H-UDI interrupts, see section 24, User Debugging Interface (H-UDI).

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