R5F72115D160FPV datasheet(136/1228 Pages) RENESAS

136 / 1228 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 May. 08, 2008 Page 112 of 1200

REJ09B0344-0200

6.3.6

Bank Number Register (IBNR)

IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow

exception. IBNR also indicates the bank number to which saving is performed next through the

bits BN3 to BN0.

IBNR is initialized to H'0000 by a power-on reset.

0000000000000000

R/W

Bit:

Initial value:

R/W:

BE[1:0]

BOVE

BN[3:0]

Bit

Bit Name

Initial

Value

R/W

Description

15, 14

BE[1:0]

R/W

These bits enable or disable use of register banks.

00: Use of register banks is disabled for all interrupts.

The setting of IBCR is ignored.

01: Use of register banks is enabled for all interrupts

except NMI and user break. The setting of IBCR is

ignored.

10: Reserved (setting prohibited)

11: Use of register banks is controlled by the setting of

IBCR.

BOVE

R/W

Enables of disables register bank overflow exception.

0: Generation of register bank overflow exception is

disabled

1: Generation of register bank overflow exception is

enabled

12 to 4

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

R5F72115D160FPV Datasheet(PDF) 136 Page - Renesas Technology Corp

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