R5F72115D160FPV datasheet(167/1228 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 May. 08, 2008 Page 143 of 1200

REJ09B0344-0200

Section 7 User Break Controller (UBC)

The user break controller (UBC) provides functions that simplify program debugging. These

functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug

programs without using an in-circuit emulator. Instruction fetch or data read/write (bus master

(CPU or DMAC) selection in the case of data read/write), data size, data contents, address value,

and stop timing in the case of instruction fetch are break conditions that can be set in the UBC.

Since this LSI uses a Harvard architecture, instruction fetch on the CPU bus (C bus) is performed

by issuing bus cycles on the instruction fetch bus (F bus), and data access on the C bus is

performed by issuing bus cycles on the memory access bus (M bus). The UBC monitors the C bus

and internal bus (I bus).

7.1

Features

1. The following break comparison conditions can be set.

Number of break channels: four channels (channels 0 to 3)

User break can be requested as the independent condition on channels 0, 1, 2, and 3.

• Address

Comparison of the 32-bit address is maskable in 1-bit units.

One of the three address buses (F address bus (FAB), M address bus (MAB), and I address bus

(IAB)) can be selected.

• Bus master when I bus is selected

Selection of CPU cycles or DMAC cycles

• Bus cycle

Instruction fetch (only when C bus is selected) or data access

• Read/write

• Operand size

Byte, word, and longword

2. Exception handling routine for user-specified break conditions can be executed.

3. In an instruction fetch cycle, it can be selected whether PC breaks are set before or after an

instruction is executed.

4. When a break condition is satisfied, a trigger signal is output from the

UBCTRG pin.

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