R5F72115D160FPV datasheet(169/1228 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 May. 08, 2008 Page 145 of 1200

REJ09B0344-0200

7.2

Input/Output Pin

Table 7.1 shows the pin configuration of the UBC.

Table 7.1

Pin Configuration

Pin Name

Symbol

I/O

Function

UBC trigger

UBCTRG

Output

Indicates that a setting condition is

satisfied on either channel 0, 1, 2, or 3 of

the UBC.

7.3

The UBC has the following registers.

Table 7.2

Channel

Abbrevia-

tion

R/W

Initial Value

Address

Access

Size

Break address register_0

BAR_0

R/W

H'00000000

H'FFFC0400

Break address mask register_0

BAMR_0

R/W

H'00000000

H'FFFC0404

Break bus cycle register_0

BBR_0

R/W

H'0000

H'FFFC04A0

Break address register_1

BAR_1

R/W

H'00000000

H'FFFC0410

Break address mask register_1

BAMR_1

R/W

H'00000000

H'FFFC0414

Break bus cycle register_1

BBR_1

R/W

H'0000

H'FFFC04B0

Break address register_2

BAR_2

R/W

H'00000000

H'FFFC0420

Break address mask register_2

BAMR_2

R/W

H'00000000

H'FFFC0424

Break bus cycle register_2

BBR_2

R/W

H'0000

H'FFFC04A4

Break address register_3

BAR_3

R/W

H'00000000

H'FFFC0430

Break address mask register_3

BAMR_3

R/W

H'00000000

H'FFFC0434

Break bus cycle register_3

BBR_3

R/W

H'0000

H'FFFC04B4

Common

Break control register

BRCR

R/W

H'00000000

H'FFFC04C0

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