R5F72115D160FPV datasheet(172/1228 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 May. 08, 2008 Page 148 of 1200

REJ09B0344-0200

7.3.3

Break Bus Cycle Register_0 (BBR_0)

BBR_0 is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user

break interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C

bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size

as the break conditions of channel 0. BBR_0 is initialized to H'0000 by a power-on reset, but

retains its previous value by a manual reset or in software standby mode or sleep mode.

0000000000000000

R/W

Bit:

Initial value:

R/W:

UBID0

CP0[1:0]

CD0[1:0]

ID0[1:0]

RW0[1:0]

SZ0[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

15, 14

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

UBID0

R/W

User Break Interrupt Disable 0

Disables or enables user break interrupt requests

when a channel-0 break condition is satisfied.

0: User break interrupt requests enabled

1: User break interrupt requests disabled

12 to 10

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

9, 8

CP0[1:0]

R/W

I-Bus Bus Master Select 0

Select the bus master when the bus cycle of the

channel-0 break condition is the I bus cycle. However,

when the C bus cycle is selected, this bit is invalidated

(only the CPU cycle).

x1: CPU cycle is included in break conditions

1x: DMAC cycle is included in break conditions

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